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library:stm32:stm32_regmap

STM32 Memory map


STM32F103 Memory map

StartENDPeripheral
0xA000_00000xA000_0FFFFSMC
0x5000_00000x5003_FFFFUSB OTG FS
0x4003_00000x4FFF_FFFFReserved
0x4002_80000x4002_9FFFEthernet
0x4002_34000x4002_7FFFReserved
0x4002_30000x4002_33FFCRC
0x4002_20000x4002_23FFFlash memory interface
0x4002_14000x4002_1FFFReserved
0x4002_10000x4002_13FFReset and clock control RCC
0x4002_08000x4002_0FFFReserved
0x4002_04000x4002_07FFDMA2
0x4002_00000x4002_03FFDMA1
0x4001_84000x4001_FFFFReserved
0x4001_80000x4001_83FFSDIO
0x4001_58000x4001_7FFFReserved
0x4001_54000x4001_57FFTIM11 timer
0x4001_50000x4001_53FFTIM10 timer
0x4001_4C000x4001_4FFFTIM9 timer
0x4001_40000x4001_4BFFReserved
0x4001_3C000x4001_3FFFADC3
0x4001_38000x4001_3BFFUSART1
0x4001_34000x4001_37FFTIM8 timer
0x4001_30000x4001_33FFSPI1
0x4001_2C000x4001_2FFFTIM1 timer
0x4001_28000x4001_2BFFADC2
0x4001_24000x4001_27FFADC1
0x4001_20000x4001_23FFGPIO Port G
0x4001_1C000x4001_1FFFGPIO Port F
0x4001_18000x4001_1BFFGPIO Port E
0x4001_14000x4001_17FFGPIO Port D
0x4001_10000x4001_13FFGPIO Port C
0x4001_0C000x4001_0FFFGPIO Port B
0x4001_08000x4001_0BFFGPIO Port A
0x4001_04000x4001_07FFEXTI
0x4001_00000x4001_03FFAFIO
0x4000_78000x4000_FFFFReserved
0x4000_74000x4000_77FFDAC
0x4000_70000x4000_73FFPower control PWR
0x4000_6C000x4000_6FFFBackup registers(BKP)
0x4000_64000x4000_67FFbxCAN1
0x4000_68000x4000_6BFFbxCAN2
0x4000_60000x4000_63FFShared USB/CAN SRAM 512 bytes
0x4000_5C000x4000_5FFFUSB device FS registers
0x4000_58000x4000_5BFFI2C2
0x4000_54000x4000_57FFI2C1
0x4000_50000x4000_53FFUART5
0x4000_4C000x4000_4FFFUART4
0x4000_48000x4000_4BFFUSART3
0x4000_44000x4000_47FFUSART2
0x4000_40000x4000_43FFReserved
0x4000_3C000x4000_3FFFSPI3/I2S
0x4000_38000x4000_3BFFSPI2/I2S
0x4000_34000x4000_37FFReserved
0x4000_30000x4000_33FFIndependent watchdog(IWDG)
0x4000_2C000x4000_2FFFWindow watchdog(WWDG)
0x4000_28000x4000_2BFFRTC
0x4000_24000x4000_27FFReserved
0x4000_20000x4000_23FFTIM14 timer
0x4000_1C000x4000_1FFFTIM13 timer
0x4000_18000x4000_1BFFTIM12 timer
0x4000_14000x4000_17FFTIM7 timer
0x4000_10000x4000_13FFTIM6 timer
0x4000_0C000x4000_0FFFTIM5 timer
0x4000_08000x4000_0BFFTIM4 timer
0x4000_04000x4000_07FFTIM3 timer
0x4000_00000x4000_03FFTIM2 timer

USB register map


The USB peripheral registers can be divided into the following groups:
• Common Registers: Interrupt and Control registers
• Endpoint Registers: Endpoint configuration and status
• Buffer Descriptor Table: Location of packet memory used to locate data buffers

All register addresses are expressed as offsets with respect to the USB peripheral registers base address 0x4000_5C00, except the buffer descriptor table locations, which starts at the address specified by the USB_BTABLE register. Due to the common limitation of APB1 bridges on word addressability, all register addresses are aligned to 32-bit word boundaries although they are 16-bit wide. The same address alignment is used to access packet buffer memory locations, which are located starting from 0x4000_6000.

USB peripheral registers base address : 0x4000_5C00
Packet buffer memory locations : 0x4000_6000

Offset Register [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 USB_EP0R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
Reset value 0
0x04 USB_EP1R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x08 USB_EP2R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x0C USB_EP3R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x10 USB_EP4R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x14 USB_EP5R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x18 USB_EP6R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x1C USB_EP7R Reserved CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
0x20-
0x3F
Reserved
0x40 USB_CNTR Reserved CTRM PMAOVRM ERRM WKUPM SUSPM RESETM SOFM ESOFM Reserved RESUME FSUSP LPMODE PDWN FRES
Reset value 0 00011
0x44USB_ISTRReservedCTRPMAOVRERRWKUPSUSPRESETSOFESOF Reserved DIR EP_ID[3:0]
Reset value 0 00000
0x48USB_FNRReservedRXDPRXDMLCKLSOF[1:0] FN[10:0]
Reset value 0 x
0x4CUSB_DADDR Reserved EF ADD[6:0]
Reset value 0
0x50USB_BTABLEReserved BTABLE[15:3] Reserved
Reset value 0

Endpoint-specific registers (USB_EPnR)

The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are enabled having the same endpoint number value. For each endpoint, an USB_EPnR register is available to store the endpoint specific information.
USB endpoint n register (USB_EPnR), n=[0..7]
Address offset: 0x00 to 0x1C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX DTOG_RX STAT_RX[1:0] SETUP EP_TYPE[1:0] EP_KIND CTR_TX DTOG_TX STAT_TX[1:0] EA[3:0]
rc_w0 t t r rw rw rc_w0 t t rw

They are also reset when an USB reset is received from the USB bus or forced through bit FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept unchanged to avoid missing a correct packet notification immediately followed by an USB reset event. Each endpoint has its USB_EPnR register where n is the endpoint identifier.

Read-modify-write cycles on these registers should be avoided because between the read and the write operations some bits could be set by the hardware and the next write would modify them before the CPU has the time to detect the change. For this purpose, all bits affected by this problem have an ‘invariant’ value that must be used whenever their modification is not required. It is recommended to modify these registers with a load instruction where all the bits, which can be modified only by the hardware, are written with their ‘invariant’ value.

The memory buffer which is currently used by the USB peripheral is defined by the DTOG bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints, DTOG_TX for ‘transmission’ isochronous endpoints, both in the related USB_EPnR register).

  • Isochronous memory buffers usage
Endpoint
type
DTOG bit
value
Packet buffer used
by the USB peripheral
Packet buffer used
by the application software
IN 0 ADDRn_TX_0 / COUNTn_TX_0
buffer description table locations.
ADDRn_TX_1 / COUNTn_TX_1
buffer description table locations.
1 ADDRn_TX_1 / COUNTn_TX_1
buffer description table locations.
ADDRn_TX_0 / COUNTn_TX_0
buffer description table locations.
OUT 0 ADDRn_RX_0 / COUNTn_RX_0
buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1
buffer description table locations.
1 ADDRn_RX_1 / COUNTn_RX_1
buffer description table locations.
ADDRn_RX_0 / COUNTn_RX_0
buffer description table locations.
library/stm32/stm32_regmap.txt · Last modified: 2019/04/06 10:43 by lhaosen