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library:proj:mi3_nrf52832
Table of Contents
MI3@NRF52832
1. Audio
1.1 Clock
fMLCK = 16 MHz fSCLK = fMLCK / 8 = 2MHz fLRCK = fSCLK / 48 = 41.67 kHz tLRCK = 24us
1.1.1 CL1026
Registers default:
offset: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0x00 : 00 F1 DF 3F 61 57 00 00 15 06 00 00 00 00 00 00 0x10 : 00 00 00 00 00 00 00 7F 03 00 3F 01 00 00 18 3F 0x20 : 3F 3F 3F 3F 3F 3F 3F 00 00 41 7D 02 81 29 A9 B4 0x62:0xBF 0x39:0x54 0x52:0x77 0x62:0xBF
Clock Settings
fMCLK: 16MHz fLRCK: fMCLK/8/48
- Digital Mic and Master Clock Control (Address 06h)
| 7 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|
| DMIC_SCLK_DIV | MCLKDIV2 | MCLKDIV1 | MCLKDIV0 | MCLKDIS |
| MCLKDIV[2:0] | MCLK Divide Ratio (from MCLK) |
|---|---|
| 000 | Divide by 1 |
| 010 | Divide by 2 |
| 011 | Divide by 3 |
| 100 | Divide by 4 |
| 101 | Divide by 6 |
- ASP Master Mode Clocking Control (Address 08h)
| 7 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|
| A_M/S | A_MMCC5 | A_MMCC4 | A_MMCC3 | A_MMCC2 | A_MMCC1 | A_MMCC0 |
A_ MMCC[5:0] x 8 x fLRCK = fMCLK(internel)
| fMCLK(MHz) | A_ MMCC[5:0] | fLRCK(kHz) |
|---|---|---|
| 6.144 | 010000(16) | 48 |
| 011000(24) | 32 | |
| 100000(32) | 24 |
Example settings:
External fMCLK: 16MHz
Mode: Slave
Sample Rate: 41.67kHz
--> MCLKDIV: 4 (Internal fMCLK = 4 MHz)
A_ MMCC: 12
--> fLRCK = 16000 / 4 / (12 * 8) = 41.67 (kHz)
[0x06]: 0000 1000 (0fh) [0x08]: 0000 1100 (0ch)
2. Appendix
2.1 Codec Output settings
External fMCLK: 16MHz External fSCLK: 2MHz External fLRCK: 41.67kHz Power: [0x01] 0xF8 [0x02] 0xDB [0x03] Clock [0x06]: 0x0f [0x08]: 0x0c
library/proj/mi3_nrf52832.txt · Last modified: 2022/05/02 00:32 (external edit)
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