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ISE主菜单命令 [File] [New Project...]
Name: SimpleTop
Location: E:\FpgaLab\SimpleTop
Working Directory: E:\FpgaLab\SimpleTop
Top-level source type: HDL
选择器件: XC6SLX25 FTG256 -2
Project: Project Name: SimpleTop Project Path: E:\FpgaLab\SimpleTop Working Directory: E:\FpgaLab\SimpleTop Description: Top Level Source Type: HDL Device: Device Family: Spartan6 Device: xc6slx25 Package: ftg256 Speed: -2 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISim (VHDL/Verilog) Preferred Language: Verilog Property Specification in Project File: Store all values Manual Compile Order: false VHDL Source Analysis Standard: VHDL-93 Message Filtering: disabled
顶层模块文件 E:\FpgaLab\SimpleTop\code\top.v,内如如下:
`timescale 1 ns / 1 ns module top ( input clk, input rst_n, output led ); reg led_r; reg [23:0] cnt; assign led = led_r; always @( posedge clk or negedge rst_n ) begin if( !rst_n ) cnt <= 0; else cnt <= cnt + 24'd1; end always @( posedge clk or negedge rst_n ) begin if( !rst_n ) led_r <= 0; else if( &cnt ) led_r <= ~led_r; else ; end endmodule
约束文件 E:\FpgaLab\SimpleTop\top.ucf,内如如下:
NET "clk" LOC = T8; NET "rst_n" LOC = R5; NET "led" LOC = T13;
操作成功的结果如下:
...... Started : "Generate Programming File". Running bitgen... Command Line: bitgen -intstyle ise -f top.ut top.ncd Process "Generate Programming File" completed successfully
成功完成后生成 E:\FpgaLab\SimpleTop\top.bit
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