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library:nordic:testonwl

WL测试

1. 接收机

1.1 I2S接口

MCLK : 16MHz
SCLK : 2MHz
LRCK : 41.67kHz
fLRCK = fSCLK / 48 = 2000(k) / 48 = 41.67 (kHz)
fSCLK = fMCLK / 8 = 16(MHz) / 8 = 2(MHz)

实际配置:

fLRCK = fMCLK / 384
fSCLK = fLRCK x 48

音频采样时间间隔:

Ts = 1/fLRCK = 384/16 = 24(us)

16采样点时长:

T16 = Ts x 16 = 384(us)

32采样点时长:

T32 = Ts x 32 = 768(us)

1.2 AK4452VN

No Pin I/O Set Effect Function
12 PS I L I2C Bus control mode (I2C pin =“H”)Control Mode Select Pin
“L”: I2c Bus serial control mode
“H”: Parallel control mode
13 I2C I H Control Mode Select Pin
“L”: 3-wire serial control mode
“H”: I2C Bus Serail control mode or Parallel control mode
11 CAD0_I2C I L Chip Address 0 Pin in I2C Bus serial control mode
8 CAD1 I L Chip Address 0 Pin in I2C Bus
9 SDA I/O I2C Data
10 SCL I I2C Clock
6 TDMO1 O NC
7 DZF O NC
1 MCLK I 16MHz1(384fs) Master Clock Input Pin
2 BICK I 2MHz1(48fs) Audio Serial Data Clock Pin
3 LRCK I fs=41.67k1 Input Channel Clock Pin
4 SDTI1 I
28 LDOE I H Enable Internal LDO
32 PDN I From MCU(pull down) Power-Down & Reset Pin
When “L”, Powerd-down and the control registers are reset to default state
FSEL I H Digital Filter:
Short Delay Sharp Roll-Off
Digital Filter select Pin
“L”: Sharp Roll-Off, “H”: Short Delay Sharp Roll-Off
DIF/TDMI I H Mode 1:
I2S Slave
MCLK=256/384fs
LRCK=L/H
BICK >= 48fs
Referent to: page 16
Audio Data Format Select Pin
“L”: MSB justified, “H”: I2S
CKS I GND

1 : 实测数值

2. 发射机

2.1 频道和频率

CHF1(MHz)F2(MHz)
124252475
224222472
324022450
424472478
524282453
624302461
724332467
824362469
924132456
1024162458
1124072464
1224052439
1324192444
1424102442

2.2 I2S接口

测量值

MCLK : 16MHz
SCLK : 2MHz
LRCK : 41.67kHz
fLRCK = fSCLK / 48 = 2000(k) / 48 = 41.67 (kHz)
fSCLK = fMCLK / 8 = 16 (MHz)

配置:

fLRCK = fMCLK / 384
fSCLK = fLRCK x 48
-> fMCLK = fSCLK x 8 = fLRCK x 48 x 8 

音频采样时间间隔:

tLRCK = 1/fLRCK = 384/16 = 24(us)

16采样点时长:

T16 = Ts x 16 = 384(us)

32采样点时长:

T32 = Ts x 32 = 768(us)

2.3 AK5720VT

Pin I/O Set Effect Function
GSEL I L 0dB Input Gain Select Pin
“L”: 0dB, “H”: +15dB
LRCK I fs=41.67k1 Channel Clock Pin
MCLK I 16MHz1(384fs) Master Clock Input Pin
BICK I 2MHz1(48fs) Audio Serial Data Clock Pin
PDN I From MCU Reset & Power Down Pin
“L”: Reset & Power down, “H” : Normal operation
FSEL I H Digital Filter:
Short Delay Sharp Roll-Off
Digital Filter select Pin
“L”: Sharp Roll-Off, “H”: Short Delay Sharp Roll-Off
DIF/TDMI I H Mode 1:
I2S Slave
MCLK=256/384fs
LRCK=L/H
BICK >= 48fs
Referent to: page 16
Audio Data Format Select Pin
“L”: MSB justified, “H”: I2S
CKS I GND Mode Select Pin

1 : 实测数值

library/nordic/testonwl.txt · Last modified: 2022/05/02 00:32 (external edit)