Demo: FPGA Project with Microblaze

参考：ISE 14.7 新建工程

参考：Create a Microblaze Core

在ISE中打开FPGA工程，在主菜单使用 [Source] [Add Source..] 命令，选择第二节中生成的CPU软核(xxx.xmp).

• 修改顶层模块(top.v)，加入引用Microblaze的代码及相关端口修改，修改后的代码如下：

`timescale 1ns / 1ps

module top
(
input               CLK_IN,
input               RSTN_IN,
output              LED,
output              EXT10,
input               EXT12,
output              EXT14,
output              EXT16
);

// Clock & reset signal remap
wire                clk;
wire                rst_n;

// Core connections
wire                uart_tx;
wire                uart_rx;
wire                uart_gnd;
wire                led;

assign clk          = CLK_IN;
assign rst_n        = RSTN_IN;
assign LED          = led;

assign EXT16        = uart_gnd;
assign EXT14        = uart_tx;
assign uart_rx      = EXT12;
assign EXT10        = clk;


(* BOX_TYPE = "user_black_box" *)
cpu CPU_i (
    .uart_rx        ( uart_rx       ),
    .uart_tx        ( uart_tx       ),
    .led            ( led           ),
    .clk            ( clk           ),
    .rst_n          ( rst_n         )
);

endmodule

• 修改约束文件(top.ucf)

NET "CLK_IN"        LOC = T8;
NET "RSTN_IN"       LOC = R5;
NET "LED"           LOC = T13;

NET "EXT16"         LOC = C9;
NET "EXT14"         LOC = A9;
NET "EXT12"         LOC = B10;
NET "EXT10"         LOC = A10;

NET "EXT12"         PULLUP;

• 编译

......
Checking platform address map ...

Initializing Memory...
Running Data2Mem with the following command:
data2mem -bm "implementation/cpu_bd" -p xc6slx25ftg256-2 -bt
"implementation/cpu.bit"  -bd "bootloops/microblaze_0.elf" tag microblaze_0  -o
b implementation/download.bit 
Memory Initialization completed successfully.


Process "Generate Programming File" completed successfully

在ISE(ISE Project Navigator)中，选中CPU，[Export Hardware Design To SDK with Bitstream]： 软件workspace设置：E:\FpgaLab\MicroBlaze\ProcessorForLx25\Demo\SDK\workspace

Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
Conversion to XML complete.
xdsgen -inp cpu.xmp -report SDK\SDK_Export\hw/cpu.html  -make_docs_local
Release 14.7 - xdsgen EDK_P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Generated Block Diagram.
Rasterizing microblaze_0.jpg.....
Rasterizing mb_plb.jpg.....
Rasterizing ilmb.jpg.....
Rasterizing dlmb.jpg.....
Rasterizing dlmb_cntlr.jpg.....
Rasterizing ilmb_cntlr.jpg.....
Rasterizing lmb_bram.jpg.....
Rasterizing RS232.jpg.....
Rasterizing LEDS.jpg.....
Rasterizing clock_generator_0.jpg.....
Rasterizing mdm_0.jpg.....
Rasterizing proc_sys_reset_0.jpg.....
Rasterizing cpu_blkd.jpg.....
Report generated.
Report generation completed.
Done!

在SDK(Xilinx Software Development Kit)中使用菜单命令 [File] [New] [Application Project],填写项目名称：demo
使用工程模板 [Peripheral Tests]
SDK自动生成项目代码，主函数在 testperiph.c 中的定义。

1. 使用Jtag加载配置文件到FPGA
2. 在SDK中编译并运行程序
3. 通过串口接收打印信息

在SDK中，主菜单工具 [Xilinx Tools] → [Program FPGA],填写参数：
Bitstream: system.bit
BMM File: system_bd_bmm
microblaze_0: demo.elf

15:20:40 INFO  : FPGA configured successfully with bitstream "E:/FpgaLab/MicroBlaze/ProcessorForLx25/Demo/SDK/workspace/MicroZed_hw_platform/download.bit"