Create a Microblaze Core

Create a workspace of microblaze.

• Run XPS(Xilinx Platform Studio), [Create New Project Using Base System Builder]
• Setup project

Project File: E:\MicroBlaze\ProcessorForLx25\Demo\cpu.xmp
Select an Interconnect Typpe: PLB System

Board: I would like to create a system for a custom board
spartan6  xc6slx25 ftg256 -2
Single-Processor System
Reference Clock Frequency: 50 MHz
System Clock Frequency: 50 MHz

Add Device...
UART -> Baud Rate 115200
GPIO -> GPIO Data Width: 1

• System Summary

LEDS  0x81400000 0x8140FFFF
RS232 0x84000000 0x8400FFFF
......

• Modify Clock module according to board parameters

Set Clock...
For module: clock_generator_0:
CLKIN:24576000
CLKOUT0:49152000

Set RS232 Baund Rate...
For module RS232:
UART Lite Baud Rate : 115200

• Modify Port names

## At [Ports] tab → [External Ports] Section

Alterate Port Names to:
clk
rst_n
led
uart_tx
uart_rx
......
Modify the cpu.ucf if necessary.

• Set Design language to Verilog

On main menu, click [Project] → [Project Options] → [Design Flow]
Set HLD as Verilog

• To Generate

On main menu, click [Hardware] → [Generate Netlist] to run the process. After a few minutes, you will get the follow if there is no error.

Total run time: 165.00 seconds
"Running synthesis..."
cd synthesis & synthesis.cmd
"xst -ifn "system_xst.scr" -intstyle silent"
"Running XST synthesis ..."
PMSPEC -- Overriding Xilinx file
<D:/Xilinx/14.7/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file
<D:/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6.acd>
"XST completed"
Done!

1. 硬件修改(XPS)后更新FPGA设计

在XPS中，[Generate Netlist]

2. 硬件修改(XPS)后跟新SDK

在XPS中，[Export Design]
在SDK中，修改system.mss