====== STM32 Memory map ====== ---- ====== STM32F103 Memory map ====== ^Start^END^Peripheral^ |0xA000_0000|0xA000_0FFF|FSMC| |0x5000_0000|0x5003_FFFF|USB OTG FS| |0x4003_0000|0x4FFF_FFFF|Reserved| |0x4002_8000|0x4002_9FFF|Ethernet| |0x4002_3400|0x4002_7FFF|Reserved| |0x4002_3000|0x4002_33FF|CRC| |0x4002_2000|0x4002_23FF|Flash memory interface| |0x4002_1400|0x4002_1FFF|Reserved| |0x4002_1000|0x4002_13FF|Reset and clock control RCC| |0x4002_0800|0x4002_0FFF|Reserved| |0x4002_0400|0x4002_07FF|DMA2| |0x4002_0000|0x4002_03FF|DMA1| |0x4001_8400|0x4001_FFFF|Reserved| |0x4001_8000|0x4001_83FF|SDIO| |0x4001_5800|0x4001_7FFF|Reserved| |0x4001_5400|0x4001_57FF|TIM11 timer| |0x4001_5000|0x4001_53FF|TIM10 timer| |0x4001_4C00|0x4001_4FFF|TIM9 timer| |0x4001_4000|0x4001_4BFF|Reserved| |0x4001_3C00|0x4001_3FFF|ADC3| |0x4001_3800|0x4001_3BFF|USART1| |0x4001_3400|0x4001_37FF|TIM8 timer| |0x4001_3000|0x4001_33FF|SPI1| |0x4001_2C00|0x4001_2FFF|TIM1 timer| |0x4001_2800|0x4001_2BFF|ADC2| |0x4001_2400|0x4001_27FF|ADC1| |0x4001_2000|0x4001_23FF|GPIO Port G| |0x4001_1C00|0x4001_1FFF|GPIO Port F| |0x4001_1800|0x4001_1BFF|GPIO Port E| |0x4001_1400|0x4001_17FF|GPIO Port D| |0x4001_1000|0x4001_13FF|GPIO Port C| |0x4001_0C00|0x4001_0FFF|GPIO Port B| |0x4001_0800|0x4001_0BFF|GPIO Port A| |0x4001_0400|0x4001_07FF|EXTI| |0x4001_0000|0x4001_03FF|AFIO| |0x4000_7800|0x4000_FFFF|Reserved| |0x4000_7400|0x4000_77FF|DAC| |0x4000_7000|0x4000_73FF|Power control PWR| |0x4000_6C00|0x4000_6FFF|Backup registers(BKP)| |0x4000_6400|0x4000_67FF|bxCAN1| |0x4000_6800|0x4000_6BFF|bxCAN2| |0x4000_6000|0x4000_63FF|Shared USB/CAN SRAM 512 bytes| |0x4000_5C00|0x4000_5FFF|USB device FS registers| |0x4000_5800|0x4000_5BFF|I2C2| |0x4000_5400|0x4000_57FF|I2C1| |0x4000_5000|0x4000_53FF|UART5| |0x4000_4C00|0x4000_4FFF|UART4| |0x4000_4800|0x4000_4BFF|USART3| |0x4000_4400|0x4000_47FF|USART2| |0x4000_4000|0x4000_43FF|Reserved| |0x4000_3C00|0x4000_3FFF|SPI3/I2S| |0x4000_3800|0x4000_3BFF|SPI2/I2S| |0x4000_3400|0x4000_37FF|Reserved| |0x4000_3000|0x4000_33FF|Independent watchdog(IWDG)| |0x4000_2C00|0x4000_2FFF|Window watchdog(WWDG)| |0x4000_2800|0x4000_2BFF|RTC| |0x4000_2400|0x4000_27FF|Reserved| |0x4000_2000|0x4000_23FF|TIM14 timer| |0x4000_1C00|0x4000_1FFF|TIM13 timer| |0x4000_1800|0x4000_1BFF|TIM12 timer| |0x4000_1400|0x4000_17FF|TIM7 timer| |0x4000_1000|0x4000_13FF|TIM6 timer| |0x4000_0C00|0x4000_0FFF|TIM5 timer| |0x4000_0800|0x4000_0BFF|TIM4 timer| |0x4000_0400|0x4000_07FF|TIM3 timer| |0x4000_0000|0x4000_03FF|TIM2 timer| ===== USB register map ===== ---- The USB peripheral registers can be divided into the following groups:\\ • Common Registers: Interrupt and Control registers\\ • Endpoint Registers: Endpoint configuration and status\\ • Buffer Descriptor Table: Location of packet memory used to locate data buffers\\ All register addresses are expressed as offsets with respect to the USB peripheral registers base address **0x4000_5C00**, except the buffer descriptor table locations, which starts at the address specified by the USB_BTABLE register. Due to the common limitation of APB1 bridges on word addressability, all register addresses are aligned to 32-bit word boundaries although they are 16-bit wide. The same address alignment is used to access packet buffer memory locations, which are located starting from **0x4000_6000**. USB peripheral registers base address : **0x4000_5C00**\\ Packet buffer memory locations : **0x4000_6000** ^ Offset ^ Register ^ [31:16] ^ 15 ^ 14 ^ 13 ^ 12 ^ 11 ^ 10 ^ 9 ^ 8 ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | 0x00 | **USB_EP0R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | ::: | Reset value | ::: | 0 |||||||||||||||| | 0x04 | **USB_EP1R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x08 | **USB_EP2R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x0C | **USB_EP3R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x10 | **USB_EP4R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x14 | **USB_EP5R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x18 | **USB_EP6R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x1C | **USB_EP7R** ^ Reserved | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | 0x20-\\ 0x3F ^ Reserved |||||||||||||||||| | 0x40 ^ USB_CNTR ^ Reserved | CTRM | PMAOVRM | ERRM | WKUPM | SUSPM | RESETM | SOFM | ESOFM ^ Reserved ||| RESUME | FSUSP | LPMODE | PDWN | FRES | | ::: | Reset value | ::: | 0 ||||||||:::|||0|0|0|1|1| |0x44|**USB_ISTR**^Reserved|CTR|PMAOVR|ERR|WKUP|SUSP|RESET|SOF|ESOF^ Reserved |||DIR| EP_ID[3:0] |||| | ::: | Reset value | ::: | 0 ||||||||:::|||0|0|0|0|0| |0x48|**USB_FNR**^Reserved|RXDP|RXDM|LCK|LSOF[1:0]|| FN[10:0] ||||||||||| | ::: | Reset value | ::: | 0 |||||x||||||||||| |0x4C|**USB_DADDR**^ Reserved |||||||||EF| ADD[6:0] ||||||| | :::| Reset value | ::: |||||||||0 |||||||| |0x50|**USB_BTABLE**^Reserved| BTABLE[15:3] ||||||||||||^ Reserved ||| | :::| Reset value | ::: |0|||||||||||||:::||| ==== Endpoint-specific registers (USB_EPnR) ==== The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are enabled having the same endpoint number value. For each endpoint, an USB_EPnR register is available to store the endpoint specific information.\\ USB endpoint n register (**USB_EPnR**), n=[0..7]\\ Address offset: 0x00 to 0x1C\\ Reset value: 0x0000\\ ^ 15 ^ 14 ^ 13 ^ 12 ^ 11 ^ 10 ^ 9 ^ 8 ^ 7 ^ 6 ^ 5 ^ 4 ^ 3 ^ 2 ^ 1 ^ 0 ^ | CTR_RX | DTOG_RX | STAT_RX[1:0] || SETUP | EP_TYPE[1:0] || EP_KIND | CTR_TX | DTOG_TX | STAT_TX[1:0] || EA[3:0] |||| | rc_w0 | t | t || r | rw || rw | rc_w0 | t | t || rw |||| They are also reset when an USB reset is received from the USB bus or forced through bit FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept unchanged to avoid missing a correct packet notification immediately followed by an USB reset event. Each endpoint has its USB_EPnR register where n is the endpoint identifier. Read-modify-write cycles on these registers should be avoided because between the read and the write operations some bits could be set by the hardware and the next write would modify them before the CPU has the time to detect the change. For this purpose, all bits affected by this problem have an ‘invariant’ value that must be used whenever their modification is not required. It is recommended to modify these registers with a load instruction where all the bits, which can be modified only by the hardware, are written with their ‘invariant’ value. The memory buffer which is currently used by the USB peripheral is defined by the DTOG bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints, DTOG_TX for ‘transmission’ isochronous endpoints, both in the related USB_EPnR register). * Isochronous memory buffers usage ^ Endpoint\\ type ^ DTOG bit\\ value ^ Packet buffer used\\ by the USB peripheral ^ Packet buffer used\\ by the application software ^ | IN | 0 |ADDRn_TX_0 / COUNTn_TX_0\\ buffer description table locations. |ADDRn_TX_1 / COUNTn_TX_1\\ buffer description table locations.| | ::: | 1 |ADDRn_TX_1 / COUNTn_TX_1\\ buffer description table locations. |ADDRn_TX_0 / COUNTn_TX_0\\ buffer description table locations.| | OUT | 0 |ADDRn_RX_0 / COUNTn_RX_0\\ buffer description table locations. |ADDRn_RX_1 / COUNTn_RX_1\\ buffer description table locations.| | ::: | 1 |ADDRn_RX_1 / COUNTn_RX_1\\ buffer description table locations. |ADDRn_RX_0 / COUNTn_RX_0\\ buffer description table locations.|