====== ISE 14.7 新建工程 ======
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===== 1. 开始新建工程 =====

  ISE主菜单命令 [File] [New Project...]
  
===== 2. 填写工程名称、路径等信息 =====

Name: **SimpleTop** \\
Location: **E:\FpgaLab\SimpleTop** \\
Working Directory: **E:\FpgaLab\SimpleTop** \\
Top-level source type: **HDL** \\
  
===== 3. 设置项目参数，包括器件型号、工具链等 =====

  选择器件: XC6SLX25 FTG256 -2
  
===== 4. 检查Project Summary =====

<code>
Project:
    Project Name: SimpleTop
    Project Path: E:\FpgaLab\SimpleTop
    Working Directory: E:\FpgaLab\SimpleTop
    Description: 
    Top Level Source Type: HDL

Device:
    Device Family: Spartan6
    Device:        xc6slx25
    Package:       ftg256
    Speed:         -2

    Top-Level Source Type: HDL
    Synthesis Tool: XST (VHDL/Verilog)
    Simulator: ISim (VHDL/Verilog)
    Preferred Language: Verilog
    Property Specification in Project File: Store all values
    Manual Compile Order: false
    VHDL Source Analysis Standard: VHDL-93

    Message Filtering: disabled
</code>

===== 5. 添加顶层模块 =====

顶层模块文件 **E:\FpgaLab\SimpleTop\code\top.v**,内如如下:
<code>
`timescale 1 ns / 1 ns

module top
(
input     clk,
input     rst_n,
output    led
);

reg        	    led_r;
reg  [23:0]     cnt;

assign led = led_r;

always @( posedge clk or negedge rst_n )
begin
    if( !rst_n )
        cnt <= 0;
    else
        cnt <= cnt + 24'd1;
end

always @( posedge clk or negedge rst_n )
begin
    if( !rst_n )
        led_r <= 0;
    else if( &cnt )
        led_r <= ~led_r;
    else ;
end

endmodule
</code>

===== 6. 添加约束文件 =====

约束文件 **E:\FpgaLab\SimpleTop\top.ucf**,内如如下:
<code>
NET "clk"	LOC = T8;
NET "rst_n" 	LOC = R5;
NET "led" 	LOC = T13;
</code>

===== 7. 编译并生成加载文件 =====

操作成功的结果如下：
<code>
......

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f top.ut top.ncd

Process "Generate Programming File" completed successfully
</code>
成功完成后生成 **E:\FpgaLab\SimpleTop\top.bit**

===== 8. 加载配置文件到FPGA中测试 =====


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**全文完**